Aditya Devaskar
Design Engineer II @Cadence | MTech in VLSI @COEP |
6.2
Years of Experience
Education
atharva college of engineering ace
Companies
tata
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Email (Verified)
adXXXXXXXXXXXXXXXXXXXom
Experience
2018 - Present
tata
platform planning and design engineer
Experience
6 Skills
Design
Python
R
Research and Development (R&D)
Very-Large-Scale Integration (VLSI)
vlsi
Education
2014 - 2018
atharva college of engineering ace
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