Profile

Aliaksei Chapyzhenka

Software Engineer at SiFive

15.1

Years of Experience

Education

belarusian state university of informatics and radioelectronics, belarusian state university of informatics and radioelectronics

Companies

sifive, signal laboratories inc., arteris, intel, intel, intel labs wireless communications lab, intel labs wireless communications lab, intel corporation intel communications group, neotec semiconductor ltd., telecommunication company of molodechno mtk, laboratory of new technologies ntl, radioplant sputnik rd center

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Email

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Experience

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    2018 - Present

    sifive

    Sr Staff Engineer

    Building future HDL IR and compiler infrastructure github.com/llvm/circt. Developed format for capturing integration intent with reusable IP blocks, models, interfaces, registers; and SoC tools: github.com/sifive/duh. Developed DSP library, code generation and profiling tools for RISC-V Vector processor. Work in RISC-V foundation technical groups.

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    2018 - 2018

    signal laboratories inc.

    Principal Engineer

    Architecture, design and RTL implementation of wireless baseband processor based on RISC-V architecture and custom instruction extensions; coarse grain reconfigurable systolic datapath optimized for complex DSP workload. Development of new distributed MIMO multicarrier wireless PHY algorithms, implementation in GnuRadio, Octave, C, ASM. RF design and prototyping including antennas and helical filters.

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    2014 - 2018

    arteris

    SW Director, Principal Engineer

    Leading software development team in design of configuration and generation tool for heterogeneous cache coherent SoC interconnect IP. Development of customer facing Web UI, tools and libraries. Developed new high-level Hardware Description Language, compiler and tools. NoC performance modeling framework in C++.

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    2011 - 2014

    intel

    Senior Design Engineer

    Development of VLSI Soft-IP collateral, configuration / generation software (TCL, Perl) for several configurable SoC infrastructure / fabric IPs. Was responsible on architecture and Verilog RTL design of custom external memory interface. Feature enhancements and porting of several Verilog / VHDL RTL blocks for new multi-standard, mixed signal wireless IC. Perl scripting / automation of design and documentation flows.

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    2008 - 2011

    intel

    Systems Architect

    Custom base-band DSP processor extended with elastic re-configurable systolic array technology: - Technical leadership; - Architecture, instruction set specification / design; - Design-time development and processor generation software tools (Perl); - C++ firmware development, compiler tools architecture; Frequency domain ATSC demodulator: - Leadership through research, algorithm, MATLAB model development and performance evaluation / optimization.

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    2006 - 2008

    intel labs wireless communications lab

    SoC Architect

    Architected design-time configurable, run-time programmable / reconfigurable array data-streaming machine IP for multi radio based SoCs. - Author micro-architecture specifications - Ensure systems requirements are met - Analyze applications and incorporate key technologies and standards - Technical leadership of RTL design, compiler tool-chain and application development teams to perform joint optimization of the complexity / programmability trade-offs involving hardware / software partitioning - SoC power efficiency architecture exploration research

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    2005 - 2006

    intel labs wireless communications lab

    Senior VLSI Design Engineer

    Programmable OFDM specific DSP engine: - Architecture definition - Verilog RTL design - Simulation, synthesis, SystemVerilog functional verification, FPGA prototyping - IEEE802.11a protocol porting

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    2003 - 2005

    intel corporation intel communications group

    Senior Hardware Engineer

    Building SoC design / verification productivity system for Broadband Wireless IEEE 802.16 (WiMAX) project: - Pre-silicon chip validation environment, and tools development - Build custom Multi-FPGA full chip prototyping platform - Embedded DSP processor microarchitecture optimizations

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    2001 - 2003

    neotec semiconductor ltd.

    Digital IC Designer

    ARM based embedded multimedia platform SoC project: - Visual Multi Processor Unit with LCD controller and graphic acceleration functions - Integrated memory subsystem - Peripheral Processor Unit with SD MMC card functions - System and processor architecture, Verilog RTL, logic synthesis, static timing analysis, FPGA prototyping and performance analysis, Forth firmware development - Work as Project Manager in building up an corporative IP reuse and documentation infrastructure

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    1997 - 2001

    telecommunication company of molodechno mtk

    Head of design group

    Embedded system development - Schematic, Verilog RTL, telecommunication and voice application firmware - System and embedded 16-bit stack processor architecture, FPGA implementation - Russian mobile phone systems: "Kart"​, "Altai"​, "VoLeMoT"​, "Vilia" protocol, schematic, PCB, hardware and software implementation

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    1996 - 1997

    laboratory of new technologies ntl

    Application Engineer

    Engaged in development of new Stack microprocessor, testing, benchmarking of DSP algorithms, architecture documentation. Developing Forth compiler, library and applications.

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    1994 - 1996

    radioplant sputnik rd center

    Electronic designer

    I developed the schematic and Forth firmware for the new mobile phone station using the stack processor. Implementation of radio modem and voice processing algorithms. Result: additional consumer functions, serial production at the plant, BOM cost reduction

Experience

17 Skills

Algorithms

architecture

Automation

Communication

Design

GitHub

Hardware

infra

Infrastructure

Integration

IP

Prototyping

soc

Software Engineer

ui

Web

Wireless

Education

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    1996 - 1999

    belarusian state university of informatics and radioelectronics

    PhD Study

    Digital Signal Processing

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    1989 - 1994

    belarusian state university of informatics and radioelectronics

    Master’s Degree

    Radio Engineering

Colleagues at sifive

Andrew Lenharth

Principal Engineer

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Bo-Hong LAI

AI Application Framework Engineer

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Chris Lattner

President, Engineering and Product

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Dai Haruki

Sr.Staff Performance Architect

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Aliaksei Artamonau

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