About

Mayank Chakraverty is a Senior Staff Engineer at ams AG with over 6 years of experience in Process Design Kit (PDK) Development & Validation for Cadence & Agilent PDKs. He has a strong understanding of Design Rule Check (DRC) design rules and Features Extract (FE) Booleans, which he utilizes to work on test case development and regression testing of Assura & Calibre design rule decks. Mayank is also experienced in verification of ADS standalone PDKs and has worked on a number of CMOS, BiCMOS, RF, SOI, power MOS, and photonics-integrated CMOS PDKs. Mayank's technical skills include Cadence Virtuoso-XL vIC6.1.6, Cadence Assura DRC/LVS and Mentor Calibre DRC/LVS, Cadence Spectre Circuit Simulator, Agilent ICCAP, Programming in R, Cadence SKILL Language Programming, and PERL Programming. He is currently working as a Senior Staff Engineer - Analog Design Enablement at ams AG and has previously worked as a Member of Technical Staff - PDK Development at Maxim Integrated and as a Principal Engineer - Design Enablement at GlobalFoundries. Mayank holds a Doctor of Philosophy - PhD degree from VIT, where he conducted research in the field of nanotechnology. He also holds a Master of Technology - MTech degree from VIT, where he specialized in nanoelectronics, and a Master of Science (MS) degree from Manipal University, where he studied microelectronics. Mayank completed his B.E. in Electronics and Communication Engineering from Anna University and Vels Srinivasa College of Engineering and Technology, Chennai. He also completed his AISSCE from Donyi Polo Vidya Bhawan, Itanagar, India, and his AISSE from Govt. Higher Secondary School, Miao, Arunachal Pradesh. Mayank's tech stack includes experience in software engineering and testing. With his extensive experience in PDK development and validation, he is a valuable asset to any team working in the field of analog design enablement.