About

Murali Yanamandala is an experienced FPGA Design Engineer currently working at Intel. With over 8 years of relevant experience, he has a strong background in RTL design, FPGA prototyping, and image and video processing algorithms. He is well-versed in feature detection, panorama making, contrast enhancement algorithms such as CLAHE, noise filtering, and communication protocols such as Ethernet 1G, SPI, and UART. Murali also has sound knowledge in timing closure, image processing, and FPGA architecture. In addition to his technical expertise, Murali has completed a course on machine learning from Coursera and has worked on several projects in linear regression, logistic regression, ANN, and CNN. He is also familiar with unsupervised algorithms such as K-Means clustering and PCA. Murali has previously worked at einfochips as a Senior Engineer, where he was responsible for RTL design, architecture, DDR4 IP, and PCIe Gen 3 EP Intel IP. He has also worked at Mirafra as a Member of Technical Staff, where he worked on AI at Xilinx (XHD), 5G Phy development at Samsung (SRIB) Electronics, and FPGA prototyping at Analog Devices India (ADI). Murali holds a Master of Technology in Digital Electronics and Communication System from JNTU, where he graduated in 2012. He also holds a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from the same university, where he graduated in 2006. Murali's tech stack includes CNN, image processing, ML, software engineering, and AI. With his extensive experience and expertise, Murali is an asset to any team he works with.