About

Rajnish Aggarwal is a Deep Learning Compiler Engineer at NVIDIA with a keen interest in high performance algorithm design for Deep Learning frameworks and its generalization to make optimization passes for modern compilers. He completed his Masters in Electrical and Computer Engineering from Carnegie Mellon University, where he worked in the research group of Professor Tze Meng Low. Rajnish's course work at CMU also focused on optimization in general. Prior to joining NVIDIA, Rajnish worked as an R&D Engineer out of the Synopsys India office in Bangalore, where he was a part of the Native Low Power team, responsible for implementing the IEEE UPF (Unified Power Format) features in VCS (Verilog Compiler and Simulator) along with carrying out time and memory optimizations in the existing code. Rajnish's education history includes a Bachelor's degree in Electrical, Electronics and Communications Engineering from IIT Kharagpur, an AISSCE from Sri Guru Harkishan Public School, and an AISSE from St. Joseph's Convent School, Pathankot, Punjab, India. He also holds a Master's degree in Electrical and Computer Engineering from Carnegie Mellon University. Apart from his work, Rajnish loves to learn about and implement Storage and Distributed file systems. He is open to exploring new ideas in his field and is always happy to connect with like-minded individuals. His technical skills include Deep Learning and Research Scientist. With 5.86 years of relevant experience, Rajnish is a dedicated and skilled engineer with a passion for optimizing algorithms and frameworks to improve performance.