About

Ram Bamdhamravuri is an experienced Hardware Performance Engineer with a strong background in computer engineering. He is currently working at IBM, where he is responsible for SMP cache hierarchy modeling for present and future platforms of System Z. Ram has over 8 years of relevant experience in the field and has previously worked with Intel and Visteon Corporation. Ram's technical expertise includes programming languages such as CUDA, OpenMP, MPI, Verilog HDL, C, C++, Python, and Perl. He is also skilled in simulation tools like Cadence Virtuoso, Cadence Spectre, Synopsys Design Vision, ModelSim, Quartus, and Max Plus II. Additionally, he has experience working with packages like Gem5, Xilinx Virtex-5 FPGA kit, and Qt. During his time at Intel, Ram worked as a PDG architecture intern and was responsible for pre-silicon performance validation of next-generation Intel platforms. He also automated the test environment to generate the statistics of the tests and root cause the failures. Ram also developed the internal architecture simulator to enhance the interface between graphics core emulator and the uncore part. He modified and enhanced the GPU's injector for the internal simulator. At Visteon Corporation, Ram worked as a Software Engineer and was part of the Electronics Innovation Team. He developed innovative user personalized features in an automobile. Ram holds a Master of Science (M.S.) degree in Computer Engineering from the University of Wisconsin-Madison. He also has a B.E. (Hons) degree in ECE, Electronics & Communication Engineering from the Birla Institute of Technology and Science, Pilani. Ram has a solid understanding of software engineering and is highly proficient in Python.